Flip-chip semiconductor packaging technology has been introduced in early 1960s by the IBM company, which is characterized in using solder bumps for electrically connecting a semiconductor chip to a substrate instead of using general gold wires as compared with wire-bonding technology. The flip-chip technology yields significant advantages, for example increasing packaging density to reduce the size of package element, and improving electrical performance as not requiring relatively lengthy metallic wires. Accordingly, there has been proposed control-collapse chip connection (C4) technology to use high temperature solder on a ceramic substrate. Recently due to increase in high-density, high-speed and low-cost requirements for semiconductor elements, and in response to gradual reduction of volume of electronic products, it is greatly developed to mount a flip-chip element (such as a silicon chip) on a low-cost organic circuit board (such as a printed circuit board or substrate) and fill a gap between the silicon chip and the organic circuit board with underfill epoxy resin so as to reduce thermal stresses produced by mismatch in thermal expansion between the silicon chip and the organic circuit board.
In the current flip-chip technology, a plurality of electrode pads are formed on a surface of a semiconductor IC (integrated circuit) chip, and corresponding contact pads are formed on an organic circuit board, such that solder bumps or other conductive adhesive materials can be adequately disposed between the chip and the circuit board. The chip is mounted on the circuit board in a face-down manner that an active surface of the chip faces the circuit board. The solder bumps or other conductive adhesive materials provide electrical input/output (I/O) connection and mechanical connection between the chip and the circuit board.
FIG. 1 shows a conventional flip-chip element. As shown in FIG. 1, a plurality of metallic bumps 11 are formed on electrode pads 12 of a chip 13, and a plurality of pre-solder bumps 14 made of a solder material are formed on contact pads 15 of an organic circuit board 16. Under a reflow temperature sufficient to make the re-solder bumps 14 melt, the re-solder bumps 14 are reflowed to the corresponding metallic bumps 11 to form solder joints 17. Further in the fabrication processes, a gap between the chip 13 and the circuit board 16 can be filled with an underfill resin material 18, so as to reduce mismatch in thermal expansion between the chip 13 and the circuit board 16 and decrease stresses for the solder joints 17.
However, the foregoing package fabrication processes uses a large amount of Sn—Pb materials for electrical connection. The Sn—Pb materials have relatively high costs, making fabrication costs increased and causing an environmental problem due to the materials containing Pb. Moreover, an electrical connection path of conductive circuits is relatively lengthy in the above package, thereby not able to improve overall electrical performance.
In light of the above problem, there has been developed a new semiconductor packaging technique named “bumpless build-up lamination (BBUL)” technique. The BBUL technique does not use solder bumps, but employs copper connections for electrically connecting the chip to various layers of the package structure in a high-speed manner.
Although the BBUL technique can solve the problem of chip electrical connection, in BBUL packaging processes due to mismatch in coefficient of thermal expansion (CTE) between a semiconductor material (such as a chip) and a receiving base material, breakage or cracks of layout circuits may be caused. As a result, an additional underfilling process is required to fill an encapsulating resin in a gap between the chip and the receiving base material. However, the underfilling process not only increase fabrication steps but also easily leads to a problem such as flashes due to difficulty in control quality stability in fabrication; the flashes would contaminate the chip and thus adversely affect reliability of the fabrication processes. Moreover, the encapsulating resin is different in material from a subsequent insulating layer required for circuit stacking, such that the underfilling process not only increase the fabrication steps but also easily causes a delamination problem. In addition, during resin underfilling, due to the size of the gap between the chip and the base material, the encapsulating resin is not easy to effectively fill the small gap and thus causes voids in the gap, which would lead to a popcorn effect during a thermal cycle of a subsequent circuit stacking process and a subsequent reliability test. This makes the quality stability of the BBUL package unsatisfactory and difficult to control, thereby not able to be widely accepted.
Furthermore, along with advanced development of electronic industries, electronic products are accordingly made with multiple functions and high performances. In order to achieve the high integration and miniaturization requirements of semiconductor packages, heat produced by operation of semiconductor chips would be greatly increased. If the heat produced from the requirements of semiconductor packages, heat produced by operation of semiconductor chips cannot be timely and effectively dissipated, the performances and lifetime of the semiconductor chips would be severely affected. Additionally, general semiconductor packages do not have effective shielding effects, which may be easily subject to external electromagnetic and noise interference and thus operation thereof would be adversely affected.